1. Field of the Invention
This invention relates generally to ferroelectric memories. More particularly, the present invention relates to those memories employing an array of one-transistor, one-capacitor ("1T/1C") ferroelectric memory cells.
2. Related Application Information
This application is related to the following applications assigned to the assignee of the present invention, which are all hereby specifically incorporated by this reference:
Ser. No. 08/970452, entitled "REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY";
Ser. No. 08/970520, entitled "MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY";
Ser. No. 08/970518, entitled "REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY";
Ser. No. 08/970519, entitled "SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY";
Ser. No. 08/970454, entitled "COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY";
Ser. No. 08/970521, entitled "SENSE AMPLIFIER LATCH DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY";
Ser. No. 08/970522, entitled "PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY"; and
Ser. No. 08/970448, entitled "PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY".
3. Description of the Prior Art
The first designs with ferroelectric capacitors utilized memory cells containing two transistors and two ferroelectric capacitors, ("2T/2C"). Ferroelectric 2T/2C memory products are shown and described in the 1996 Ramtron International Corporation FRAM.RTM. Memory Products databook, which is hereby incorporated by reference. A 2T/2C memory is also described in U.S. Pat. No. 4,873,664 entitled "Self Restoring Ferroelectric Memory", which is also hereby incorporated by reference. The 2T/2C memory cells were arranged in a physical layout such that the transistors and the ferroelectric capacitors were adjacent in the cell.
FIG. 1 is a schematic diagram of a 2T/2C memory cell and also represents the relative proximity of the physical layout of the elements. Ferroelectric memory cell 10 includes a first transistor M1 coupled to a first ferroelectric capacitor CC, and a second transistor M2 coupled to a second ferroelectric capacitor CCb. Ferroelectric capacitors CC and CCb store complementary polarization states, which define a single data state of memory cell 10. The plate line PL, which is coupled to one side of the ferroelectric capacitors CC and CCb runs parallel to the word line WL, which is coupled to the gates of the two transistors M1 and M2. In the arrangement of FIG. 1, the signal propagation delay along the plate line PL across one cell is insignificant compared to the delay in transferring data from the cell to the complementary bit lines BL and BLb, which are coupled to the source/drains of transistors M1 and M2. In the schematic of FIG. 1, the connection between the common electrodes for capacitors CC and CCb is a plate line wire PL. This plate line wire is a highly conductive material, generally a metal conductor. Also, the physical layout of memory cell 10 places these elements in close proximity to each other.
A timing diagram for the operation of a 2T/2C memory cell such as cell 10 is shown in FIG. 3. The control signals necessary to develop charge on the complementary bit lines BL and BLb are the word line signal WL and the plate line signal PL. The word line waveform 12 is a pulse that transitions from ground to the VCC supply voltage. The plate line waveform 14, 16 can either be a shorter or longer pulse, depending upon the desired sensing method. Initially, the word line and plate line waveforms are at ground potential. At time t.sub.0, the word line waveform is taken high to the VCC power supply voltage level, which turns on transistors M1 and M2 and electrically couples the ferroelectric capacitors CC and CCb to the bit lines BL and BLb, respectively. Once the high voltage level has been established on the word line, the plate line is pulsed to "pole" the ferroelectric capacitors at time t.sub.1. Plate line waveform 14 is used for the "up-down" sensing method. With reference to the hysteresis loop 38 of FIG. 10, the "up-down" sensing method senses the charge developed moving from point 1 to point 2 to point 3 of the "switched" ferroelectric capacitor, minus the charge developed moving from point 3 to point 2 back to point 3 in the "unswitched" ferroelectric capacitor. Note that waveform 14 is brought low to ground potential at time t.sub.2. At time t.sub.3 the sense amplifiers (not shown in FIG. 1) are enabled and the differential charge on the bit lines BL and BLb can be sensed and converted into a valid logic state. Plate line waveform 16 is used for the "up-only" sensing method. With reference again to the hysteresis loop 38 of FIG. 10, the "up-only" sensing method senses the charge developed moving only from point 1 to point 2 in the "switched" ferroelectric capacitor minus the charge moving from point 3 to point 2 of the "unswitched" ferroelectric capacitor. Note that plate line waveform 16 remains high at times t.sub.2 and t.sub.3. At time t.sub.3 the sense amplifiers are enabled and the differential charge on the bit lines can be sensed and again converted into a valid logic state. Although the charge in each case is slightly different, the charge from the switched ferroelectric capacitor in cell 10 is always larger than the charge from the unswitched capacitor, so that the correct data state can be sensed.
In the full array of memory cells 10, bit lines are paired as true/complement and connected as illustrated in FIG. 4. Each block 10 is a 2T/2C memory cell as shown in previous FIG. 1. In the arrangement of FIG. 4, there is a multiplicity of paired plate lines PL0 through PLN and word lines WL0 through WLN extending in the word or row direction. There is a corresponding multiplicity of pairs of true/complement bit lines BL0/BLb0 through BLN/BLbN in the column or bit direction.
Using the physical layout corresponding to the array of FIG. 4, the data pattern along the bit lines is always in pairs of true complement data. Therefore, no matter what logical data pattern is written into the array, the bit line data pattern as described by "1's" and "0's" representing the actual high and low voltages on the bit lines is described completely by the pattern "10" plus its complement "01". This is not to be confused with the logical data states of "1" and "0" that refers to a pair of bit lines, such as BL0 and BLb0. The "1" or "0" referred to below represents the high "1" and low "0" voltage on each pair of bit (BL0-BLN) and bit bar (BLb0-BLbN) bit lines shown in FIGS. 1 and 4. Any other larger array of cells repeats this basic pattern. Assuming eight columns for the array shown in FIG. 4, corresponding to 16 bit/bit bar pairs, the pattern combinations could be, for example, 1010101010101010, 0101010101010101, 1001100110011001 or 0110011001100110. Because of the nature of the cell layout with true complement data per cell there is never an accumulated pattern of all "1's" or all "0's" or of isolated bits such as all 1's with a single zero or its complement as illustrated by the following 16 bit sequences: 1111111101111111 or 0000000010000000. Again, each individual "1" or "0" represents the voltage on an individual bit line wire.
Patterns such as that described above having single "0's" or "1's" in a field of opposite polarity can be created, however, in a 1T/1C memory design, depending on the chip architecture. These patterns create cumulative noise on the bit lines within an array. When the sense amplifiers are latched, noise generated through capacitive coupling between bit lines reduces the operating margin of the single bit line of opposite polarity. A schematic of a 1T/1C DRAM cell 20 coupled to a single bit line BL for a single storage location is shown in FIG. 5. One side of conventional oxide capacitor CC is connected to the access transistor M1 and the other side is connected to a node 22 that is common to all memory cells in a DRAM array. The common node 22 is usually at a potential of one half of the VCC power supply voltage, for example 2.5 volts for a five volt power supply voltage.
The ferroelectric version of the 1T/1C DRAM memory cell 20 of FIG. 5 is shown in FIG. 2. Ferroelectric memory cell 18 also includes a single access transistor M1, which is coupled to a ferroelectric capacitor CC. A single word line WL is coupled to the gate of access transistor M1 and a single bit line BL is coupled to the source/drain of access transistor M1. Instead of a common node 22 as in the DRAM cell 20, ferroelectric memory cell 18 includes an individual active plate line PL per word line as shown in FIG. 2.
The noise problem described above with reference to a 1T/1C array occurs when an "open bit line" architecture is used. In this configuration, all the true bits are assembled on one side of the sense amplifier and all the complement bit lines are on the opposite side of the sense amplifier. The open bit line architecture is illustrated in FIG. 6. The array shown in FIG. 6 utilizes the DRAM 1T/1C memory cell 20 of FIG. 5. The open bit line array of FIG. 6 includes bit lines BL0 through BLN and word lines WL0 through WLN in the bottom half of the array, and complementary bit lines BLb0 through BLbN and complementary word lines WLC0 through WLCN in the top half of the array. The bit lines and complementary bit lines are coupled to a row of sense amplifiers SA0 through SAN. In the open bit line configuration it is possible that when a word line is accessed all the data on one side of the sense amplifiers could be all "1's" with a single zero as indicated in the 16 bit sequences described above, generating noise. This noise problem was solved by utilizing a "folded bit line" architecture, described below.
The folded bit line array configuration is illustrated in FIG. 9 utilizing the DRAM memory cell 24 shown in FIG. 7 and the DRAM reference cell 26 shown in FIG. 8. The capacitors, access transistors, word lines, and bit lines of memory cell 24 and reference cell 26 are shown in the approximate locations on the physical layout on the chip. In the folded bit line approach shown in the array of FIG. 9, the array is comprised of odd and even word lines indicated by WLO and WLE, respectively, extending from word lines WLO0 and WLE0 through WLON and WLEN. Whenever an odd or even word line is activated, data is read from the memory cells 24 onto every other bit line. At the same time an even or odd word line is accessed an (opposite) odd, WRO, or even, WRE, reference word line is accessed to apply a reference level to the opposite bit line. Utilizing this folded bit line approach, it can be observed that the data pattern on the respective bit lines is similar to that of the 2T/2C design, previously described with respect to FIG. 4. Each bit line pair BL/BLb alternates data as described above for the 2T/2C design, thus eliminating the cumulative noise pattern described for the open bit line architecture of FIG. 6.
The design of ferroelectric memories is inexorably progressing to ever higher densities. To remain cost competitive with alternative memory technologies, new ferroelectric memories will be based on the 1T/1C ferroelectric memory cell shown in FIG. 2. In a ferroelectric 1T/1C design, there is a reference word line and many corresponding memory word lines. This is the opposite of a 2T/2C design, where each memory cell has in essence its own built-in reference in the pairing of true complement data. This common reference line in a folded bit line architecture for a 1T/1C ferroelectric memory is again analogous to the 1T/1C DRAM designs shown in FIG. 9. The difference between the two being that the ferroelectric memory has an additional wire added for control of the plate line and rewriting the polarization state in the ferroelectric capacitor, rather than a fixed-potential common electrode as in DRAMs. There have been approaches suggested for ferroelectric 1T/1C memory designs that utilize a common electrode such as that of DRAMs, illustrated by common node CP in FIGS. 7 and 8. Each of these approaches, however, have associated problems such as leakage of the internal cell nodes requiring refresh, power up noise issues, and complex circuitry needed to mitigate the aforementioned problems.
Assuming that a 1T/1C folded bit line architecture is used, two new noise issues are introduced that are unique to a ferroelectric memory array. These noise issues result from both the physical interconnections with each memory row having an individual plate line per word line or shared plate line per pair of word lines, and in the sequence of operation.
The first noise problem results from the common plate line along a word line that allows noise to propagate from cell to cell. This first noise problem is data pattern dependent. The noise patterns created are analogous to that described above for the open bit line architecture DRAM. This problem does not exist in 1T/1C DRAM memory cells since the common second electrode of the memory capacitor is shared for the entire array. This common electrode in DRAMs acts as a filter capacitor with a low resistance path to propagate the noise induced into the plate when a word line is accessed. As described earlier there have been proposals for the same architecture (common electrode for the entire array) to be used with ferroelectric designs. There are, however, significant operating problems with these approaches that make their implementation impractical.
The second noise issue results from the operating voltages of the bit lines during the reading of information from the memory cells prior to sensing. In most high density memory designs the sense amplifier used to determine the voltage difference on the bit lines resulting from reading the cells is the cross coupled type as shown in FIG. 21 (sense amplifier 30). Often the constraints of the physical layout pitch of the memory cell in the bit line or column direction require that the nodes labeled "LATCH P" and "LATCH N" are actually a common wire shared across many columns. During the reading of information the bit line voltage can exceed the threshold voltage of a P-channel or N-channel transistor, i.e. the point at which the transistor begins conducting current between source and drain. When these bit line voltages exceed the threshold voltages of the transistors, noise can be transmitted through the cross-coupled P-channel and N-channel devices to the common latch nodes (LATCH P and LATCH N). This noise can then affect the signal margin in other columns.
What is desired, therefore, is a 1T/1C ferroelectric memory architecture, interconnection approach, operating methodology, sensing control sequence, and layout configuration that minimizes the noise issues set forth above.